Introduction
1
1. Instruction Set Nomenclature
6
2. Cpu Registers Located In The I/O Space
8
2.1. Rampx, Rampy, And Rampz
8
2.2. Rampd
8
2.3. Eind
8
3. The Program And Data Addressing Modes
9
3.1. Register Direct, Single Register Rd
9
3.2. Register Direct - Two Registers, Rd And Rr
9
3.3. I/O Direct
10
3.4. Data Direct
10
3.5. Data Indirect
11
3.6. Data Indirect With Pre-Decrement
11
3.7. Data Indirect With Post-Increment
12
3.8. Data Indirect With Displacement
12
3.9. Program Memory Constant Addressing Using The Lpm, Elpm, And Spm Instructions
13
3.10. Program Memory With Post-Increment Using The Lpm Z+ And Elpm Z+ Instruction
13
3.11. Store Program Memory Post-Increment
14
3.12. Direct Program Addressing, Jmp And Call
14
3.13. Indirect Program Addressing, Ijmp And Icall
15
3.14. Extended Indirect Program Addressing, Eijmp And Eicall
15
3.15. Relative Program Addressing, Rjmp And Rcall
16
4. Conditional Branch Summary
17
5. Instruction Set Summary
18
6. Instruction Description
24
6.1. Adc – Add With Carry
24
6.2. Add – Add Without Carry
25
6.3. Adiw – Add Immediate To Word
26
6.4. And – Logical And
27
6.5. Andi – Logical And With Immediate
28
6.6. Asr – Arithmetic Shift Right
29
6.7. Bclr – Bit Clear In Sreg
30
6.9. Brbc – Branch If Bit In Sreg Is Cleared
32
6.10. Brbs – Branch If Bit In Sreg Is Set
33
6.11. Brcc – Branch If Carry Cleared
34
6.12. Brcs – Branch If Carry Set
35
6.13. Break – Break
36
6.14. Breq – Branch If Equal
36
6.15. Brge – Branch If Greater Or Equal (Signed)
37
6.16. Brhc – Branch If Half Carry Flag Is Cleared
38
6.17. Brhs – Branch If Half Carry Flag Is Set
39
6.18. Brid – Branch If Global Interrupt Is Disabled
40
6.19. Brie – Branch If Global Interrupt Is Enabled
41
6.20. Brlo – Branch If Lower (Unsigned)
42
6.21. Brlt – Branch If Less Than (Signed)
43
6.22. Brmi – Branch If Minus
44
6.23. Brne – Branch If Not Equal
45
6.24. Brpl – Branch If Plus
46
6.25. Brsh – Branch If Same Or Higher (Unsigned)
47
6.26. Brtc – Branch If The T Bit Is Cleared
48
6.27. Brts – Branch If The T Bit Is Set
49
6.28. Brvc – Branch If Overflow Cleared
50
6.29. Brvs – Branch If Overflow Set
51
6.30. Bset – Bit Set In Sreg
52
6.31. Bst – Bit Store From Bit In Register To T Bit In Sreg
53
6.32. Call – Long Call To A Subroutine
54
6.33. Cbi – Clear Bit In I/O Register
55
6.34. Cbr – Clear Bits In Register
56
6.35. Clc – Clear Carry Flag
57
6.36. Clh – Clear Half Carry Flag
57
6.37. Cli – Clear Global Interrupt Enable Bit
58
6.38. Cln – Clear Negative Flag
59
6.39. Clr – Clear Register
60
6.40. Cls – Clear Sign Flag
61
6.41. Clt – Clear T Bit
62
6.42. Clv – Clear Overflow Flag
62
6.43. Clz – Clear Zero Flag
63
6.44. Com – One’s Complement
64
6.45. Cp – Compare
65
6.46. Cpc – Compare With Carry
66
6.47. Cpi – Compare With Immediate
67
6.48. Cpse – Compare Skip If Equal
68
6.49. Dec – Decrement
69
6.50. Des – Data Encryption Standard
71
6.51. Eicall – Extended Indirect Call To Subroutine
72
6.52. Eijmp – Extended Indirect Jump
73
6.53. Elpm – Extended Load Program Memory
73
6.54. Eor – Exclusive Or
75
6.55. Fmul – Fractional Multiply Unsigned
76
6.56. Fmuls – Fractional Multiply Signed
77
6.57. Fmulsu – Fractional Multiply Signed With Unsigned
79
6.58. Icall – Indirect Call To Subroutine
80
6.59. Ijmp – Indirect Jump
81
6.60. In - Load An I/O Location To Register
82
6.61. Inc – Increment
83
6.62. Jmp – Jump
84
6.63. Lac – Load And Clear
85
6.64. Las – Load And Set
86
6.65. Lat – Load And Toggle
86
6.66. Ld – Load Indirect From Data Space To Register Using X
87
6.67. Ld (Ldd) – Load Indirect From Data Space To Register Using Y
89
6.68. Ld (Ldd) – Load Indirect From Data Space To Register Using Z
90
6.69. Ldi – Load Immediate
92
6.70. Lds – Load Direct From Data Space
93
6.71. Lds (Avrrc) – Load Direct From Data Space
94
6.72. Lpm – Load Program Memory
95
6.73. Lsl – Logical Shift Left
96
6.74. Lsr – Logical Shift Right
97
6.75. Mov – Copy Register
98
6.76. Movw – Copy Register Word
99
6.77. Mul – Multiply Unsigned
100
6.78. Muls – Multiply Signed
101
6.79. Mulsu – Multiply Signed With Unsigned
102
6.80. Neg – Two’s Complement
103
6.81. Nop – No Operation
104
6.82. Or – Logical Or
105
6.83. Ori – Logical Or With Immediate
106
6.84. Out – Store Register To I/O Location
107
6.85. Pop – Pop Register From Stack
108
6.86. Push – Push Register On Stack
109
6.87. Rcall – Relative Call To Subroutine
110
6.88. Ret – Return From Subroutine
111
6.89. Reti – Return From Interrupt
112
6.90. Rjmp – Relative Jump
113
6.91. Rol – Rotate Left Trough Carry
114
6.92. Ror – Rotate Right Through Carry
115
6.93. Sbc – Subtract With Carry
116
6.94. Sbci – Subtract Immediate With Carry Sbi – Set Bit In I/O Register
117
6.95. Sbi – Set Bit In I/O Register
118
6.96. Sbic – Skip If Bit In I/O Register Is Cleared
119
6.97. Sbis – Skip If Bit In I/O Register Is Set
120
6.98. Sbiw – Subtract Immediate From Word
121
6.99. Sbr – Set Bits In Register
122
6.100. Sbrc – Skip If Bit In Register Is Cleared
123
6.101. Sbrs – Skip If Bit In Register Is Set
124
6.102. Sec – Set Carry Flag
125
6.103. Seh – Set Half Carry Flag
126
6.104. Sei – Set Global Interrupt Enable Bit
127
6.105. Sen – Set Negative Flag
128
6.106. Ser – Set All Bits In Register
128
6.107. Ses – Set Sign Flag
129
6.108. Set – Set T Bit
130
6.109. Sev – Set Overflow Flag
131
6.110. Sez – Set Zero Flag
132
6.111. Sleep
132
6.112. Spm (Avre) – Store Program Memory
133
6.113. Spm (Avrxm, Avrxt) – Store Program Memory
135
6.114. St – Store Indirect From Register To Data Space Using Index X
136
6.115. St (Std) – Store Indirect From Register To Data Space Using Index Y
138
6.116. St (Std) – Store Indirect From Register To Data Space Using Index Z
140
6.117. Sts – Store Direct To Data Space
141
6.118. Sts (Avrrc) – Store Direct To Data Space
142
6.119. Sub – Subtract Without Carry
143
6.120. Subi – Subtract Immediate
144
6.121. Swap – Swap Nibbles
145
6.122. Tst – Test For Zero Or Minus
146
6.123. Wdr – Watchdog Reset
147
6.124. Xch – Exchange
148
7. Appendix A Device Core Overview
149
7.1. Core Descriptions
149
7.2. Device Tables
150
8. Revision History
161
8.1. Rev. Ds40002198B - 02/2021
161
8.2. Rev. Ds40002198A - 05/2020
161
8.3. Rev.0856L - 11/2016
161
8.4. Rev.0856K - 04/2016
161
8.5. Rev.0856J - 07/2014
161
8.6. Rev.0856I – 07/2010
161
8.7. Rev.0856H – 04/2009
162
8.8. Rev.0856G – 07/2008
162
8.9. Rev.0856F – 05/2008
162
The Microchip Website
163
Product Change Notification Service
163
Customer Support
163
Microchip Devices Code Protection Feature
163
Legal Notice
164
Trademarks
164
Quality Management System
165
Worldwide Sales And Service
166
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